1. Field of the Invention
The present invention relates to a multitask processor architecture having a single processor. More particularly, the invention relates to an architecture adapted to real time processing of tasks.
2. Discussion of the Related Art
To control multitask processes, the simplest and least expensive approach is to use a system including a processor that executes several programs, corresponding to tasks, in shared time. If a second program has to be executed by the processor while a first program is being executed, an interruption request is sent to the processor. The interruption request suspends the execution of the first program, if the second program has priority over the first. When the first program is so interrupted, the processor has to save the context of the first program with a "save context" operation. When the execution of the first program is resumed, a restore context operation restores the context that was previously saved. The restore context operation allows the first program to resume from the point at which it was interrupted.
Although multitask processor systems are relatively simple and inexpensive, they are relatively slow due to the fact that each interruption incurs overhead because several instruction cycles must be executed during interruptions. This is so, because an interruption routine is called, which saves the context and locates the starting address of the new program to be executed. Likewise, the restore context is also time consuming.
Such a system becomes unsuitable when the interruption frequency is high and when the tasks must be executed in so-called "real time".
An exemplary real time multitask system is a system designed to process television images, in which an uninterrupted flow of data is received and processed, while an uninterrupted flow of processed data is output. For image processing, pipeline architecture systems are mostly used. Such systems are able to process images at the required data flow rates, but they are very complex and expensive.
EP-A-0,503,956 describes a shared time image processing system, for decompressing video signals compressed in accordance with MPEG standards. In this system, data to be processed are transferred between a memory device, a decoding device, a movement compensation device, and a device for calculating the inverse discrete cosine transform (DCT.sup.-1). The transfers from these devices are controlled by a specific processor operating by interruptions.
Although the processor used in EP-A-0,503,956 is specifically adapted to transfer data between elements, the interruption overhead remains significant and does not allow such a system to process the presently requested data flow rates.